71. G. S. Lin and you can J. B. Kuo, “Fringing-Created Slim-Channel-Impression (FINCE) Associated Capacitance Behavior from Nanometer FD SOI NMOS Equipment Playing with Mesa-Separation Thru three-dimensional Simulator” , EDSM , Taiwan ,
72. J. B. Kuo, “Development of Bootstrap Approaches to Reduced-Current CMOS Electronic VLSI Circuits having SOC Programs” , IWSOC , Banff, Canada ,
P. Yang, “Gate Misalignment Impression Related Capacitance Conclusion out-of an effective 100nm DG FD SOI NMOS Equipment having letter+/p+ Poly Best/Base Gate” , ICSICT , Beijing, China
73. G. Y. Liu, N. C. Wang and you will J. B. Kuo, “Energy-Efficient CMOS Higher-Load Driver Circuit for the Complementary Adiabatic/Bootstrap (CAB) Way of Lowest-Fuel TFT-Lcd System Applications” , ISCAS , Kobe, The japanese ,
74. Y. S. Lin, C. H. Lin, J. B. Kuo and you can K. W. Su, “CGS Capacitance Sensation from 100nm FD SOI CMOS Gizmos having HfO2 High-k Door Dielectric Offered Straight and you may Fringing Displacement Consequences” , HKEDSSC , Hong kong ,
75. J. B. KUo, C. H. Hsu and C. P. Yang, “Gate-Misalignment Related Capacitance Choices away from good 100nm DG SOI MOS Products that have N+/p+ Top/Bottom Door” , HKEDSSC , Hong kong ,
76. Grams. Y. Liu, Letter. C. Wang and you will J. B. Kuo, “Energy-Productive CMOS Highest-Stream Driver Circuit into the Complementary Adiabatic/Bootstrap (CAB) Way of Reduced-Energy TFT-Lcd Program Software” , ISCAS , Kobe, The japanese ,
77. H. P. Chen and you may J. B. Kuo, “An effective 0.8V CMOS TSPC Adiabatic DCVS Reasoning Routine towards the Bootstrap Approach to possess Reasonable-Stamina VLSI” , ICECS , Israel ,
B. Kuo, “A book 0
80. J. B. Kuo and H. P. Chen, “A low-Voltage CMOS Load Rider towards Adiabatic and Bootstrap Approaches for Low-Power System Software” , MWSCAS , Hiroshima, Japan ,
83. Yards. T. Lin, Elizabeth. C. Sunlight, and you may J. B. Kuo, “Asymmetric Door Misalignment Effect on Subthreshold Attributes DG SOI NMOS Gizmos Given Fringing Electric Field-effect” , Electron Gizmos and you will Situation Symposium ,
84. J. B. Kuo, Elizabeth. C. Sunshine, and you may Meters. T. Lin, “Data from Gate Misalignment Influence on the new Threshold Voltage out of Twice-Gate (DG) Ultrathin FD SOI NMOS Devices Having fun with a concise Design Offered Fringing Electric Field-effect” , IEEE Electron Products for Microwave and Optoelectronic Software ,
86. E. Shen and you will J. 8V BP-DTMOS Stuff Addressable Memories Telephone Routine Produced from SOI-DTMOS Procedure” , IEEE Meeting on the Electron Devices and you can Solid state Circuits , Hong-kong ,
87. P. C. Chen and you may J. B. Kuo, “ic Logic Routine Having fun with an immediate Bootstrap (DB) Way of Reasonable-voltage CMOS VLSI” , Global Symposium toward Circuits and you can Solutions ,
89. J. B. Kuo and you can S. C. Lin, “Lightweight Description Design for PD SOI NMOS Devices Provided BJT/MOS Perception Ionization getting Liven Circuits Simulation” , IEDMS , Taipei ,
90. J. B. Kuo and you may S. C. Lin, “Compact LDD/FD SOI CMOS Tool Model Given Time Transportation and you may Thinking Heating to have Spruce Circuit Simulation” , IEDMS , Taipei ,
91. S. C. Lin and you may J. B. Kuo, “Fringing-Triggered Hindrance Decreasing (FIBL) Effects of 100nm FD beste datingside Europa SOI NMOS Gadgets with a high Permittivity Gate Dielectrics and you may LDD/Sidewall Oxide Spacer” , IEEE SOI Fulfilling Proc , Williamsburg ,
92. J. B. Kuo and you will S. C. Lin, “Brand new Fringing Electric Field-effect into the Quick-Station Impact Endurance Current away from FD SOI NMOS Gizmos having LDD/Sidewall Oxide Spacer Construction” , Hong kong Electron Products Appointment ,
93. C. L. Yang and you may J. B. Kuo, “High-Temperature Quasi-Saturation Make of High-Current DMOS Electricity Products” , Hong kong Electron Equipment Meeting ,
94. Age. Shen and you will J. B. Kuo, “0.8V CMOS Posts-Addressable-Recollections (CAM) Mobile Ciurcuit which have an instant Tag-Compare Capability Using Most PMOS Dynamic-Endurance (BP-DTMOS) Technique Considering Important CMOS Technical to own Low-Current VLSI Assistance” , Globally Symposium to your Circuits and you may Possibilities (ISCAS) Legal proceeding , Washington ,